This invention relates to an art of channel multiplex transmission by which a plurality of channels are multiplexed and transmitted, and particularly, to an art of channel multiplex demultiplex in a system for selecting particular data that have been received after multiplexing and transmission of a plurality of data.
Publication of JP-A-218233/1989 has disclosed a construction shown in FIG. 9 as a conventional channel multiplex demultiplex unit of the above-described type. It is assumed that 4 channels are multiplexed. Referring to FIG. 9, a transmission unit 108 at a transmission side combines an 8 bit parallel video signal 101 and a 1 bit serial frame signal 103 at each bit parallel into one channel signal. Then the resultant 9 bit parallel signal is converted into 10 bit parallel signal by a 9B10B coding circuit 102.
A frame signal generator 104 for generating a frame signal 103 is provided for each channel. The frame signal 103 has a common frame pattern containing a data signal.
The frame signal 103 is used for synchronization as well as for identification of each channel.
The 10 bit parallel signal of a channel output from the 9B10B encoder 102 is converted into a serial signal by 10:1 parallel/serial conversion circuit 105. The converted serial signal is further multiplexed among channels by 4:1 parallel/serial conversion circuit 106 and then input to a transmitter 107 from which the resultant transmission signal is sent to a transmission path. In a reception unit 11b, a receiver 109 receives the transmission signal, which is shifted to a serial/parallel conversion circuit 110 by a clock signal output from a hunting circuit 115. The 10 bit parallel signal corresponding to each channel is sequentially input to 10B9B decoder 111 corresponding to the channel.
A 9 bit parallel signal output from the 10B9B decoder 111 is separated into an 8 bit parallel video signal and a 1 bit frame signal. The frame signal of each channel is input to a corresponding synchronous detection circuit 112 and subjected to frame detection. The synchronous detection circuit 112 compares, for example, an input bit sequence (9 bit) with a predetermined synchronous pattern. When those patterns accord with each other, a synchronous detection signal is output. When the synchronous pattern is not detected, a report of detecting no synchronous pattern is sent to a synchronous protection circuit 114.
Among signals output from each synchronous detection circuit 112, those signals selected by a channel selection circuit 113 are input to the synchronous protection circuit 114 for frame synchronization.
When the frame synchronization is not executed in the synchronous protection circuit 114, the hunting circuit 115 shifts a phase of the clock driving the serial/parallel conversion circuit 110 by a predetermined amount. This operation is continued until the 10 bit parallel signal output from the serial/parallel conversion circuit 110 corresponds to each channel.
As aforementioned, in the conventional transmission system through channel multiplexing, 1 bit frame signal is added accompanied with a byte parallel signal of the data. The resultant coded byte becomes irregular, thus requiring its own coding.
As the decoded frame signal is serial, the frame signal is parallel converted and bit rotated (shifting the bit location in a cyclic manner, for example, inserted from LSB (low-order bit) overflowing from the MSB (high-order bit) side by the synchronous detection circuit at a reception side for comparing the bit pattern. The processing until detection of synchronization takes much time as well as requiring double bit rotate function (10B9B decoding and frame signal extraction in pattern detection for synchronous detection).